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1 for more information www.analog.com typical application features applications description hybrid step-down synchronous controller efficiency at various v in for v out = 12v all registered trademarks and trademarks are the property of their respective owners. protected by u.s. patents, including 9484799. n wide v in range: 10v to 72v (80v abs max) n soft switching for low noise operation n phase-lockable fixed frequency 200khz to 1.5mhz n 1% output voltage accuracy n r sense or dcr current sensing n programmable ccm, dcm, or burst mode ? operation n clkout pin for multiphase operation n short circuit protected n extv cc input for improved efficiency n monotonic output voltage start-up n optional external reference n 32-pin (5mm 5mm) qfn n intermediate bus converters n high current distributed power systems n telecom, datacom, and storage systems n automotive applications the lt c ? 7821 uses a proprietary architecture that merges a soft switching charge pump topology with a synchro - nous step-down converter to provide superior efficiency and emi performance compared to traditional switching architectures. in a typical 48v to 12v application, efficiency of greater than 97% is attainable with the LTC7821 switching at 500khz. the same efficiency can only be achieved with a traditional controller switching at one-third the frequency. higher switching frequencies allow the use of smaller in - ductances that yield faster transient response and smaller solution size. the LTC7821 can be easily paralleled to provide higher output currents with its accurate current sharing capability and frequency synchronization function. document feedback lt c7821 rev a m2 m3 m4 100 1f 10k 10k c out 150f 2 1k 0.1f 2h 10f 2 6.81k 0.22f v in_sense v in pins not shown in this circuit: clkout temp run hys_prgm mode/pllin track/ss m1: bsz070n08lss m2, m3: bsc032n04ls m4: bsc014n04lsi timer freq ext_ref c f ly 10f 8 fault pgood i th extv cc v fb i sns + i sns ? pgnd intv cc bg2 cb1, 0.22f sw3 boost3 tg2 mid_sense mid boost2 bg1 sw1 boost1 LTC7821 cb2 0.47f 7821 ta01a tg1 v in 36v to 72v intv cc v out 12v 20a d1 d2 d3 intv cc 8v cb3 1f pgood fault 60.4k 4.32k c mid 10f 8 2.2f 6 f sw = 500khz v out = 12v ccm i out = 20a 4.7f i out = 10a input voltage (v) 30 40 50 60 70 80 93 94 c in 100f 95 96 97 98 99 100 efficiency (%) 7821 ta01b m1
2 for more information www.analog.com pin configuration absolute maximum ratings input supply voltage (v in , v in_sense ) ....... C 0.3v to 80v top side driver voltages boost1 ................................................. C 0. 3v to 86v boost2, boost3.................................. C 0.3v to 46v switch voltages sw1 ............................................................ 0v to 80v sw3 ....................................................... C 0. 3v to 40v mid, mid_sense ....................................... C 0.3 v to 40v (boost1-sw1), (boost2-mid), (boost3-sw3) ............................................ C 0.3 v to 6v i sns + , i sns C ................................................ C 0.3 v to 40v (i sns + C i sns C ) ....................................................... 0.6v ex tv cc ...................................................... C 0.3 v to 40v temp, freq, ext_ref , v fb .................. C 0.3 v to intv cc hys_prgm , i th , run, track/ss ....... C 0. 3v to intv cc fa u lt , pgood ........................................... C 0. 3v to 80v timer, mode/pllin ............................ C 0. 3v to intv cc intv cc peak output current ................................ 100 ma operating junction temperature range (notes 2, 3, 9) .................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) aa a a a a a r r fault r ra r r r lead free finish tape and reel part marking* package description temperature range LTC7821euh#pbf LTC7821euh#trpbf 7821 32-lead (5mm 5mm) plastic qfn C40c to 125c LTC7821iuh#pbf LTC7821iuh#trpbf 7821 32-lead (5mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. order information http://www.linear.com/product/LTC7821#orderinfo lt c7821 rev a
3 for more information www.analog.com pin configuration electrical characteristics symbol parameter conditions min typ max units main control loops v in input voltage range 10 72 v output voltage range (note 4) 0.9 v in 2 C 2. 5 v v fb regulated feedback voltage i th voltage (note 5) l 0.792 0.8 0.808 v i fb feedback current (note 5) 10 50 na v reflnreg reference voltage line regulation v in = 36v to 72v (note 5) 0.003 0.02 %/v v loadreg output voltage load regulation (note 5) i th voltage = 1.2v to 0.7v i th voltage = 1.2v to 1.6v l l 0.016 C0.016 0.1 C0.1 % % g m transconductance amplifier g m i th = 1.2v; sink/source 5a (note 5) 2 mmho i vin input dc supply current normal mode shutdown precharging phase (note 6) v run = 0v, extv cc = 0v v in = 20v, v mid = v mid_sense = 9v, v sw1 = 15v, v sw3 = 10v v in = 48v, v mid = v mid_sense = 20v, v sw1 36v, v sw3 = 12v 0.5 240 40 84 ma a ma ma i vin_sense input dc supply current normal mode shutdown (note 6) v run = 0v 1 45 ma a i extvcc input dc supply current (note 6) 2.2 ma i mid mid pin current 45 a i mid_sense mid_sense pin current 4 a v uvlo v in undervoltage lockout v in ramping up l 8.8 9.4 v v uvlo_hyst uvlo hysteresis 0.28 v v sense current sense threshold v isns C = 0v l 45 50 55 mv i sns +/- isns + and isns C pin current v isns + = v isns C = 12v l 1.2 a i track/ss soft-start charge current v track/ss = 0v C9 C10 C11 a v run_on run pin on threshold v run rising l 1.1 1.3 1.6 v i run run pin current v run = 0v 1 a v run_hyst run pin hysteresis 0.1 v v ext_ref_uc ext_ref upper clamp limit (note 5) l 0.85 0.9 v v ext_ref_lc ext_ref lower clamp limit (note 5) l 0.40 0.45 v v sel_ext_ref ext_ref de-select threshold (ramping up) 1.3 v i ext_ref ext_ref pin current v ext_ref = 0.6v C150 na v temp_trip temp pin trip point, rising l 1.22 1.25 v v temp_trip_hyst temp pin trip point hysteresis 100 mv i temp temp pin current v temp = 1v 1 na v bstuvlo undervoltage lockout of (boost1-sw1), (boost2- v mid ) and (boost3-sw3) difference voltage, rising 4.4 v v bstuvlo_hyst bootstrap undervoltage lockout hysteresis 1.4 v t out temp trip timeout 100 ms the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v in_sense = 48v, v run = 5v, extv cc = 9v, ext_ref = 5.6v unless otherwise noted. lt c7821 rev a
4 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v in_sense = 48v, v run = 5v, extv cc = 9v, ext_ref = 5.6v unless otherwise noted. symbol parameter conditions min typ max units intv cc linear regulator v intvcc internal v cc regulator 10v < v in < 72v, v extvcc = 0v 5.65 5.8 5.95 v v ldoint intv cc load regulation i cc = 1ma to 50ma, v in = 12v, v extvcc = 0v C0.6 C2 % v extvcc extv cc switchover voltage extv cc ramping positive, i cc = 1ma 7 v v extvcc_hys extv cc switchover voltage hysteresis 200 mv v ldoext extv cc load regulation v extvcc = 12v, i cc = 1ma to 50ma C0.6 C2 % oscillator and phase lock loop f nom nominal frequency r freq = 68k 440 490 550 khz f low lowest frequency v freq = 0v 20 50 100 khz f high highest frequency v freq = intv cc 1400 1700 2000 khz f sync_low lowest synchronizing frequency 200 khz f sync_high highest synchronizing frequency 1500 khz i freq frequency setting current v freq = 0v l C9 C10 C11 a r mode/pllin mode/pllin resistance 250 k clkout high clkout high amplitude 2.4 v clkout low clkout low amplitude 0 v pgood output v pg1 pgood 1st trip level (with delay) v fb with respect to regulated voltage v fb ramping up (overvoltage 1st level) v fb ramping down (undervoltage 1st level) 6 C5.5 8.5 C7.5 11 C9.5 % % v pg1_hyst pgood 1st trip level hysteresis (with delay) 15 mv v pg2 pgood 2nd trip level v fb with respect to regulated voltage v fb ramping up (overvoltage 2nd level) v fb ramping down (undervoltage 2nd level) 15 C25 % % v pg2_hyst pgood 2nd trip level hysteresis 15 mv v pgl pgood voltage low i pgood = 0.6ma 0.4 0.5 v i pgood pgood leakage current v pgood = 80v 1 a capacitor balancing v timer_low voltage at timer pin to start capacitor balancing 0.5 v v timer_high voltage at timer pin to stop capacitor balancing 1.25 v i timer timer pin charge current v timer = 0.9v v timer = 2.8v l l C6 C3 C 7 C3.5 C8 C4 a a v hys_prgm capacitor balancing window comparator threshold v hys_prgm = 0v v hys_prgm = 1.2v v hys_prgm = intv cc 0.3 1.2 0.8 v v v i hys_prgm hys_prgm pin current v hys_prgm = 0v l C9 C10 C11 a v fault fault pin voltage low i fault = 0.6ma 0.2 0.4 v i fault fault leakage current v fault = 80v 1 a lt c7821 rev a
5 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = v in_sense = 48v, v run = 5v, extv cc = 9v, ext_ref = 5.6v unless otherwise noted. symbol parameter conditions min typ max units i flysrc1 current out of sw1 during capacitor balancing (v sw1 C v sw3 ) < v in /2, v sw3 = 12v 40 ma i flysnk1 current into sw1 during capacitor balancing (v sw1 C v sw3 ) > v in /2, v sw3 = 12v 6 ma i flysnk3 current into sw3 during capacitor balancing (v sw1 C v sw3 ) < v in /2, v sw3 = 12v 40 ma i flysrc3 current out of sw3 during capacitor balancing (v sw1 C v sw3 ) < v in /2, v sw3 = 12v 6 ma i mid_src current out of mid during capacitor balancing v mid < v in /2, v mid = v mid_sense = 20v v sw1 36v, v sw3 = 12v 60 ma i mid_snk current into mid during capacitor balancing v mid > v in /2, v mid = v mid_sense = 28v v sw1 36v, v sw3 = 12v 40 ma gate driver tg1,2 pull-up on resistance pull-down on resistance 2 1 b g1, 2 pull-up on resistance pull-down on resistance 2 1 tg1,2 t r tg1,2 t f tg1, tg2 transition time: rise time fall time (note 7) 4 4 ns ns b g1,2 t r bg1,2 t f bg1, bg2 transition time: rise time fall time (note 7) 4 4 ns ns t 1d tg1 off to bg1 on 45 ns t 2d tg2 off to bg2 on 20 ns t 3d tg1 off to tg2 off 25 ns t 4d bg1 off to tg1 on 40 ns t 5d bg2 off to tg2 on 20 ns t 6d bg1 off to bg2 off 20 ns t on(min) minimum on-time (note 8) 210 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC7821e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7821i is guaranteed to meet performance specifications over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: LTC7821uh: t j = t a + (p d ? 44c/w) note 4: output voltage range is guaranteed by design. for output voltage setting, read output voltage setting and minimum v out in the applications information section. note 5 : the LTC7821 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . note 6: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 7: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 8: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section) note 9: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum junction temperature may impair device reliability or permanently damage the device. lt c7821 rev a
6 for more information www.analog.com typical performance characteristics efficiency and power loss in different modes vs load current LTC7821 start-up characteristic (pre-balancing period) LTC7821 start-up characteristic t a = 25c, unless otherwise noted. shutdown current vs temperature quiescent current vs temperature shutdown (run) threshold vs temperature input voltage uvlo threshold vs temperature hys_prgm, track/ss and freq pin current vs temperature efficiency at various v in for v out = 12v lt c7821 rev a = 12v falling temperature (c) ?50 ?25 0 25 50 75 100 125 f osc = 500khz 1.10 1.15 1.20 1.25 1.30 1.35 1.40 v run (v) load current (a) 7821 g07 rising falling temperature (c) ?50 ?25 0 25 50 75 page 1 schematic 100 125 8.0 8.2 8.4 8.6 8.8 9.0 v in (v) 7821 g08 0.1 hys_prgm pin track/ss pin freq pin temperature (c) ?50 ?25 0 25 50 75 1 100 125 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10 pin current (a) 7821 g09 f sw = 500khz v out = 12v ccm i out = 20a i out = 10a input voltage (v) 30 40 100 50 60 70 80 93 94 95 96 97 98 30 99 100 efficiency (%) 7821 g02 page 1 schematic 40 ccm 50 60 70 80 90 100 0 1 2 3 dcm 4 5 6 7 8 efficiency (%) power loss (w) 7821 g01 100ms/div v in burst 50v/div timer 1v/div sw1 to sw3 20v/div mid 20v/div 7821 g02 100ms/div v in v 50v/div pgood 5v/div fault 5v/div v out 10v/div 7821 g03 temperature (c) ?50 in ?25 0 25 50 75 100 125 150 200 250 = 48v 300 350 400 i vin (a) 7821 g05 i vin i vin_sense temperature (c) ?50 ?25 v 0 25 50 75 100 125 0.2 0.3 0.4 0.5 out 0.6 0.7 0.8 0.9 1.0 1.1 1.2 supply current (ma) 7821 g06 rising
7 for more information www.analog.com typical performance characteristics timer pin current vs temperature temp pin current vs temperature regulated feedback voltage vs temperature t a = 25c, unless otherwise noted. regulated feedback voltage vs temperature oscillator frequency vs input voltage oscillator frequency vs temperature intv cc line regulation (supply from extv cc ) current sense threshold vs i th voltage switching frequency vs voltage at freq pin lt c7821 rev a 75 600 frequency (khz) 7821 g14 r freq = 68k temperature (c) ?50 ?25 0 25 50 100 75 100 125 0 100 200 300 400 500 600 125 700 800 oscillator frequency (khz) 7821 g15 extv cc voltage (v) 6 10 14 18 22 2.5 26 30 34 38 5.00 5.25 5.50 5.75 6.00 6.25 3.0 6.50 v intvcc (v) 7821 g17 i th voltage (v) 0 0.4 0.8 1.2 1.6 2 3.5 ?30 ?20 ?10 0 10 20 30 40 50 60 4.0 current sense threshold (mv) 7821 g18 freq pin voltage (v) 0 0.5 1 1.5 2 2.5 0 4.5 200.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 1800.0 switching frequency (khz) 5.0 7821 g16 5.5 v timer = 0v 6.0 6.5 7.0 7.5 i timer (a) 7821 g10 v temp = 1v temperature (c) ?50 ?25 v timer = 2.8v 0 25 50 75 100 125 0.0001 0.001 0.01 0.1 temperature (c) 1 10 i temp (na) 7821 g11 ext_ref = intv cc temperature (c) ?50 ?25 0 25 ?50 50 75 100 125 798 799 800 801 802 803 ?25 804 v fb (mv) 7821 g12 ext_ref = 0.6v temperature (c) ?50 ?25 0 25 50 0 75 100 125 599.00 599.30 599.60 599.90 600.20 600.50 v fb (mv) 25 7821 g13 r freq = 68k input voltage (v) 0 10 20 30 40 50 60 50 70 80 400 425 450 475 500 525 550 575
8 for more information www.analog.com typical performance characteristics hys_prgm voltage window vs temperature voltage at timer pin to start and stop capacitor balancing vs temperature temp pin trip voltage vs temperature line transient 10v/ms steady-state output voltage ripple of typical application load transient 2aC12aC2a of typical application short-circuit and recovery temp fault characteristic t a = 25c, unless otherwise noted. maximum current sense threshold vs common mode voltage lt c7821 rev a 75 100mv/div ac-coupled burst mode operation 100mv/div ac-coupled pulse- skipping mode 100mv/div ac-coupled 7821 g24 50s/div 100 v out 500mv/div ac-coupled i l 10a/div 7821 g25 v in = 48v v out = 12v f sw = 500khz v sense common mode voltage (v) 125 0 5 10 15 20 25 30 35 40 45.0 ?1.5 47.5 50.0 52.5 55.0 current sense threshold (mv) 7821 g19 ?1.2 ?0.9 ?0.6 ?0.3 0.0 0.3 v hys_prgm = intv cc 0.6 0.9 1.2 1.5 v mid_sns - vin/2 (v) 7821 g20 stop balancing start balancing temperature (c) ?50 v hys_prgm = 1.2v ?25 0 25 50 75 100 125 0.3 0.5 0.7 temperature (c) 0.9 1.1 1.3 1.5 v timer (v) 7821 g21 falling rising temperature (c) ?50 ?50 ?25 0 25 50 75 100 125 1.00 1.05 1.10 ?25 1.15 1.20 1.25 1.30 v temp (v) 7821 g22 1ms/div v in 10v/div mid 0 10v/div v out 100mv/div ac-coupled 7821 g23 200ms/div v out 10v/div i l 20a/div 25 pgood 5v/div 7821 g26 20ms/div temp 2v/div fault 10v/div pgood 5v/div 50 sw3 20v/div v out 20v/div 7821 g27 v in = 48v v out = 12v i load = 30ma 10s/div continuous mode
9 for more information www.analog.com pin functions mode/pllin (pin 1): mode selection or external synchro - nization input to phase detector. when external synchro - nization is not used, this pin selects the operating modes and can be tied to sgnd, to intv cc or left floating. if the pin is connected to sgnd, it enables forced continuous mode while a connection to intv cc enables pulse-skipping mode. floating the pin enables burst mode operation. for external sync, apply a clock signal to this pin. the integrated pll along with its internal compensation net - work will synchronize the internal oscillator to this clock. forced continuous mode will be enabled. clkout (pin 2) : clock output pin. this pin outputs a clock 180 out of phase with the main operating clock of the LTC7821. run (pin 3): run control input. a voltage above 1.3v turns the controller on. there is a 1a pull-up current on this pin when its voltage is below 1.3v. fault (pin 4): open drain output pin. when the signal goes low, it indicates one of the following conditions: (a) in the capacitor balancing phase, capacitors c f ly or c mid (see typical application) are not charged to v in /2. a low fault indicates an abnormal condition that is preventing c f ly or c mid from being be charged up to v in /2. (b) during normal operation, the voltage deviates from v in /2 by a window amount set by the voltage on the hys_prgm pin. (c) the die temperature exceeds its internally set limit or the ptc resistor connected as the lower leg of a resistor divider trips the temp pin threshold. during any of these condition, the track/ss pin will also be pulled low. pgood (pin 5): power good pin. this is an open drain output. pgood is pulled to ground when the voltage of the v fb pin is not within 7.5% of its set point after an internal 50s mask timer expires. it will also be pulled low when fault is tripped. timer (pin 6): charge balancing timer input. a capaci - tor connected from this pin to ground sets the amount of time allocated to charge c f ly and c mid to v in /2 during the capacitor balancing phase. it also sets the auto-retry timeout, should the capacitors fail to reach this voltage within the set time. capacitors c f ly and c mid begin and end charging when the timer voltage is between 0.5v and 1.2v , respectively. if the capacitor is balanced before the timer voltage reaches 1.2v, this voltage is reset to ground and normal operation begins. however, if the bal - ance is not reached when the voltage reaches 1.2v, then the charging of the capacitors stops and the auto-retry timeout period begins. the timer capacitor will now slew at half the rate until it reaches 4v and then resets to zero and begins to slew at 1x rate. once it reaches 0.5v, the c f ly and c mid begin to charge again and the process repeats. track/ss (pin 7): output voltage tracking and soft-start input. the LTC7821 regulates the v fb voltage to the lowest of three voltages : 0.8v , the voltage on the ext_ref pin or the voltage on the track/ss pin. an internal 10a pull- up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. alternatively, a resistor divider from another voltage supply connected to this pin allows the LTC7821 output voltage to track the other supply during start-up. ext_ref (pin 8): external reference input. a voltage ap - plied to this pin forces the v fb to regulate to this voltage. internal clamps set at 0.4v and 0.93v limit the lower and upper bounds of v fb regulation. connecting this pin to intv cc will cause the internal reference to be used for output voltage regulation. hys_prgm (pin 9): there is a 10a current flowing out of this pin. a voltage created by connecting a resistor from this pin to ground sets an equal amount of window threshold around v in /2 to a window comparator. when the voltage at mid sense is not within this window threshold, fault will be pulled low and switching will stop. c f ly and c mid will be rebalanced to half of v in before resuming normal operation. i th (pin 10): current control threshold and error amplifier compensation point. the current comparator threshold increases with its i th control voltage. freq (pin 11): frequency set pin. there is a 10a current flowing out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. lt c7821 rev a
10 for more information www.analog.com temp (pin 12): temperature sensing input. using a ptc resistor as the lower leg of a resistor divider, connect the temp pin to the common point of the divider. the ptc resistor is used to monitor a hot spot on the pcb. once it reaches the temp threshold of 1.22v, the LTC7821 stops switching for 100ms before retrying. ground this pin if not used. v fb (pin 13): error amplifier feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider across the output. i sns C (pin 14): current sense comparator input. the (C) input to the current comparator is kelvin connected to the output voltage of the controller. i sns + (pin 15): current sense comparator input. the (+) input to the current comparator is normally kelvin con - nected to the dcr sensing networks or current sensing resistor . ext v cc (pin 16): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v in whenever extv cc is higher than 6.4v. do not float or exceed 40v on this pin. pgnd (pin 17): driver power ground. connect this pin closely to the source of bottom (synchronous) n-channel mosfet m4 , the (C) terminal of c in and the (C) terminal of c vcc . bg2 (pin 18): gate drive for the bottom (synchronous) n-channel mosfet. the voltage swings from slightly below ground to intv cc . intv cc (pin 19): internal regulator output. the bottom synchronous gate driver and control circuits are powered from this regulator. bypass this pin to pgnd with a minimum of 4.7f low esr tantalum or ceramic capacitor. do not use the intv cc pin for any purpose other than described in this data sheet. sw3 (pin 20): switch node connection to inductor and one terminal of flying capacitor. voltage swing at this pin is from slightly below ground to v in /2. tg2 (pin 21): floating gate drive for second lowermost n-channel mosfet. the voltage swings equal to intv cc superimposed on the switch node voltage sw3. boost1, boost2, boost3 (pin 31, 23, 22): bootstrapped supplies to floating drivers. capacitors are connected between the boostx and swx (mid) pin. voltage swing at the boost1 pin is from (v in /2 + intv cc ) to (v in + in- tv cc ). voltage at the boost2 pin is at (v in /2 + intv cc ). voltage swing at the boost3 pin is from intv cc to (v in /2 + intv cc ). bg1 (pin 24): floating gate drive for second uppermost n-channel mosfet. the voltage swings between (v in /2 + intv cc ) and v in /2. mid (pin 25): half supply from v in . do not use this to source current. connect a bypass capacitor from this node to pgnd. mid sense (pin 26): half supply monitor. provides kelvin sensing input for the comparator that monitors the voltage between mid sense and ground. an rc filter can be added from mid to this pin to filter out noise. v in_sense (pin 27) : v in kelvin sensing input. allows an internal v in /2 to be generated for LTC7821 control circuit usage. for a cleaner supply, an rc filter can be added from v in to this pin. v in (pin 28): main input supply. bypass this pin to pgnd with a capacitor. sw1 (pin 29): switch node connection to one terminal of flying capacitor. voltage swing at this pin is from v in /2 voltage to v in . t g1 (pin 30): floating gate drive for uppermost n-channel mosfet. the voltage swings equal to intv cc superimposed on the switch node voltage sw1. sgnd (exposed pad, pin 33): signal ground. all small- signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. exposed pad must be soldered to the pcb, providing a local ground for the control components of the ic, and be tied to the pgnd pin under the ic. pin functions lt c7821 rev a
11 for more information www.analog.com block diagram ? + ? + ? + ? + ? + + ? ? ? + + ? + + ? + ? + ? + ? + ? + ? + lt c7821 rev a v/i r4 intv cc pgood 7821 bd01 1.5m v in /2 1.5m 0.5v sleep 1.2v run ss 1a ea 10a 1 51k 1.2v switch logic and anti-shoot through run mode/sync detect s q r osc r2 c3 0.6v 0.5v 3k 500k 500k mode/pllin intv cc icmp irev pll sync slope comp c2 4v fcnt bursten balen balen freq clkout i th sns ? sns + timer 3.5a hys_prgm track/ss run ext_ref v fb pgnd mid_sense temp fault extv cc 3.5a boost3 tg2 sw3 bg2 boost1 tg1 sw1 boost2 bg1 mid 10a bal v in /2 capacitor balancing circuit v in bst cap charger v in bst cap charger v in v in_sense bst cap charger 0.8v ref intv cc v a v b 0.74v v c 1.075 0.925 x0.825 0.86v 0.66v uv ov 1.2v 6.48v 100ms timeout 1.2v v in ext linear reg r1 shdn 1.2v shdn int linear reg
12 for more information www.analog.com operation capacitor balancing phase during initial power up, the voltage across the flying capaci - tor (c f ly ) and c mid are measured. if either of these voltages are not at v in /2, the timers capacitor will be allowed to charge up. when the timer capacitors voltage reaches 0.5v , internal current sources to bring c f ly voltage to v in /2 are turned on. after the c f ly voltage has reached v in /2, c mid will then be charged to v in /2. the track/ss pin is pulled low during this duration and all external mosfets are shut off. the fault pin will not be pulled low during this initial power up. if the voltages across c f ly and c mid reach v in /2 before the timer capacitor s voltage reaches 1.2v, the track/ss will be released and allowed to charge up. the timer pin will reset to ground and remain there. normal operation will begin (see figure 1a). if, however, the c f ly or c mid voltage is not at v in /2 when v timer reaches 1.2v , the internal current sources will be turned off and the timer capacitor will be charged at half the initial rate until it reaches 4v . timer will then be reset to zero, and the LTC7821 will repeat the above process again until c fly and c mid are at v in /2(see figure 1b). during normal operation, only c mid is monitored for devia - tion away from v in /2 by a window amount set by a resistor connected from hys_prgm to ground. the voltage across this resistor sets the same amount of window threshold above and below v in /2. if v cmid leaves this voltage win - dow, all switching will stop and the track/ss pin will be pulled low . corresponding internal current sources will be turned on to bring c f ly and c mid voltages back to v in /2. fault will be pulled low and released once the balancing is complete. during this balancing period, pgood will also be pulled low. the track/ss pin is also allowed to charge up upon the completion of balancing. connecting hys_prgm to intv cc sets the window threshold to 0.8v around v in /2. (see figure 2) main control loop once the capacitor balancing phase is completed, normal operation begins. mosfets m1 and m3 are turned on when the clock sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. mosfets m2 and m4 are then turned on. the peak inductor figure 1. charge balancing during power up with (a) balancing completed within one timer period and (b) more than one timer period figure 2. charge balancing during normal operation with (a) balancing completed within one timer period and (b) more than one timer period lt c7821 rev a timer track/ss 0v 0.5v 1.2v (a) (b) 7821 f01 fault timer fault 0.5v 1.2v track/ss fault timer track/ss 7821 f02 0.5v 1.2v (a) timer (b) track/ss 0v 0.5v 1.2v 4v fault
13 for more information www.analog.com operation current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v reference, which in turn causes the i th voltage to increase until the aver - age inductor current matches the new load current. after mosfet s m1 and m3 have turned off, mosfets m2 and m4 are turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator i rev , or the beginning of the next cycle. during the switching of m1/m3 and m2/m4 , capacitor c f ly is alternately connected in series with or parallel to c mid . the voltage at mid will be approximately at v in /2. intv cc /extv cc power power for the bootstrap drivers and bottom mosfet and most internal circuitry is derived from the intv cc pin. when the extv cc pin is grounded or tied to a voltage less than 7v, an internal 5.8v linear regulator supplies intv cc power from v in . if extv cc is taken above 7v, this linear regula- tor is turned off and another 5.8v linear regulator turns on to provide the int v cc power from extv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source, resulting in an overall increase in system efficiency. bootstrap capacitor refresh each of the three uppermost mosfet drivers is biased from its respective floating bootstrap capacitor, cb1 to cb3, which are refreshed during switching through a charge pump configuration consisting of diodes d1 to d3 and the external mosfets. during the charge balancing phase or light load condition when switching may stop for extended amount of time, the voltage across the bootstrap capacitor may decrease sufficiently that the gate drive voltage is not optimal. un - dervoltage detectors monitor the voltage across each of the bootstrap capacitors. when any of them goes below 3v , an internal current source of 1ma will be turned on to charge that bootstrap capacitor through the upper plate of the capacitor. a 1ma sinking source that is connected to the bottom plate of the bootstrap capacitor will also be turned on to sink away this current. this ensures a net zero residual current at the bottom plate capacitor node, hence avoiding any impact on the bias condition of that node. when cb1 and cb2/cb3 reach 4.3v and 4.47v respectively, the refreshing stops. when cb2 and cb3 need to be refreshed, all switching stops. shutdown and start-up (run and track/ss pins) when the run pin is below 1.3v , the intv cc linear regulator along with all the internal circuitry that is powered from this supply, is disabled. the main control loop will also be disabled. releasing the run pin will allow the internal 1a current source to pull this pin up, thus enabling the part. the run pin can also be driven directly by logic but ensure that this voltage does not exceed the absolute maximum rating of 6v. the slew rate of the output voltage v out can be controlled by the voltage on the track/ss pin. when the voltage on the track/ss is less than the internal reference of 0.8v (or ext_ref if this feature is invoked), the LTC7821 regulates the v fb voltage to the track/ss voltage instead of to the reference. this allows the track/ss pin to be used to program the soft-start period by connecting an external capacitor from the track/ss pin to sgnd. an internal 10a pull-up current charges this capacitor, creat - ing a voltage ramp on the track/ss pin. as the track/ ss voltage rises linearly from 0v to the reference voltage (and beyond), the output voltage v out rises smoothly from zero to the final value. alternatively, the track/ss pin can be used to cause the start-up of v out to track that of another supply. typically this requires connecting to the track/ss pin an external resistor divider from the other supply to ground (see application information section). light load current operation (burst mode operation, pulse-skipping mode, or continuous conduction) the LTC7821 can be enabled to enter high efficiency burst mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.6v (e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. lt c7821 rev a
14 for more information www.analog.com when the controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifier output, ea, will decrease the voltage on the i th pin. when the i th voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and all external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the external mosfets on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (irev) turns off the bottom external mosfet m4 and m2 just before the inductor current reaches zero, preventing it from revers - ing and going negative. thus, the controller operates in discontinuous operation. in for ced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the LTC7821 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator i cmp may remain tripped for several cycles and force the external mosfets m1 and m3 to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or output capacitance to maintain low output ripple voltage. in addition, it will also require larger boost capacitance and balancing ca - pacitance (c f ly and c mid ) since the refresh rate is lower. the switching frequency of the LTC7821s controller can be selected using the freq pin. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 50khz to 1.7mhz. there is a 10a current flowing out of the freq pin, so the user can program the controllers switching frequency with a single resistor to sgnd. a phase-locked loop (pll) is integrated on the LTC7821 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller operates in forced continuous mode when it is synchronized. the pll loop filter network is integrated inside the LTC7821. the phase-locked loop is capable of locking any frequency within the range of 200khz to 1.5mhz . the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. temperature monitoring when the LTC7821 die temperature reaches 150 c, switching stops and track/ss pin is pulled low. charge balancing is also disabled. the LTC7821 can provide hotspot monitoring via the temp pin. by using a ptc thermistor as the lower leg of a resistor divider and connecting the common point of this divider to the temp pin, the voltage increases drastically when the temperature reaches beyond the curie point of the ptc thermistor as shown in figure 3. the character - istic of the ptc thermistor is shown in figure 4. when the temp pin reaches 1.22v , all switching stops for 100ms. operation lt c7821 rev a
15 for more information www.analog.com operation the voltage on the track/ss pin and fault is pulled low and is released after 100ms (figure 5) if the voltage on the temp pin goes below 1.1v during this 100ms timeout. if the temp pin voltage remains above 1.1v , the timeout period will be extended until the voltage drops below 1.1v. the temperature that is use to trigger the hotspot protec - tion will determine the thermistor selection. this tem - perature will be the curie point of the thermistor, which is often defined as having two times its resistance at 25c. with the curie point resistance of the thermistor known, r2 curie , the upper resistance, r1, can be selected by the following equation: r1 = r2 curie (v ext C 1.22) 1.22 power good (pgood pin) when v fb pin voltage is not within 10% of the internal 0.8v reference or the reference set by ext_ref , the pgood pin is pulled low. the pgood pin is also pulled low when the run pin is below 1.3v or when the LTC7821 is in the figure 5. temperature trip characteristic figure 3. temperature monitoring setup soft-start or tracking phase. the pgood pin will flag power good immediately when the v fb pin is within the 10% of the reference window. however, there is an internal 50s power bad mask when v fb goes out the 10% window. the pgood pin is allowed to be pulled up by an external resistor to sources of up to 80v. fault ( fault pin) during initial power up of the LTC7821 or when enabling the part via the run pin, the fault pin will not be pulled low even when c f ly and/or c mid needed to be rebalanced to v in /2. but during normal operation, when rebalancing is needed, the fault will be pulled low. another condition that causes the fault to go low is thermal shutdown, either caused by the internal die temperature reaching 150c or the voltage at temp pin reaching 1.22v. the fault pin is allowed to be pulled up by an external resistor to sources of up to 80v. figure 4. characteristic of a thermistor 7821 f05 lt c7821 rev a temperature of thermistor (c) 25c curie point 7821 f04 temp trip level = 1.22v temp swx track/ss fault 100ms r1 r2 temp 7821 f03 LTC7821 v ext ptc resistance of thermistor (log )
16 for more information www.analog.com applications information the typical application on the first page is a basic LTC7821 application circuit. the LTC7821 can be con - figured to use either dcr (inductor resistance) sensing or resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption, and accuracy . dcr sensing is popular because it saves an expensive current sensing resistor and is more power efficient, especially in high current applications. however, a current sensing resistor provides the most accurate current limit for the application. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used). next c f ly , c mid , and the power mosfets are selected, followed by the input and output capacitors. in addition to the power level, switching frequency plays a role in selecting the balancing capacitance (c f ly and c mid ) and the inductance of the inductor. isns + and isns C pins the isns + and isns C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 36v . both isns pins are high impedance inputs with small leakage currents of less than 1.2a . when the isns pins ramp up from 0v to 2.4v, small base currents flow out of the isns pins. when the isns pins ramp down from 36v to 2v, the small base cur - rents flow into the isns pins. the high impedance inputs to the current comparators allow accurate dcr sensing. however , care must be taken not to float these pins during normal operation. filter components mutual to the sense lines should be placed close to the LTC7821, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 6). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 7b ), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. resistor current sensing the hybrid architecture of the LTC7821 generates a voltage rail of half the v in supply to the step-down control loop. therefore the current ripple calculation and its operating duty cycle is referred to the voltage at the mid pin which is approximately at v in/2 . a typical sensing circuit using a discrete resistor is shown in figure 7a. r sense is chosen based on the required output current. the current comparator has a maximum threshold of 50mv and its inputs have a common mode range of 0v to 36v . the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to- peak ripple current, i l . to calculate the sense resistor value, use the equation: r sense = 50mv i (max ) + i l 2 because of possible pcb noise in the current sensing loop, the ac current sensing ripple of v sense = i l ? r sense also needs to be verified in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 10mv v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications, for duty cycles less than 40%. for applications where the inductors ripple current could be greater than 50% and operating at 750khz and above, the sense resistors parasitic inductance has to be taken into consideration since its contribution is no longer negligible. figure 6. sense lines placement with sense resistor 7821 f06 lt c7821 rev a r sense c out to sense filter, next to the controller
17 for more information www.analog.com applications information in an application where the sense resistor s parasitic in - ductance contribution is negligible, a small rc filter placed near the ic is enough to reduce the effects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 10 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns . however, the same rc filter with minor modifications can be used to extract the resistive component of the current sense signal in the presence of significant parasitic inductance in the sense resistor. for example, figure 8 illustrates the voltage waveform across a 1m sense resistor with a 2010 footprint for the 12v/20a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.3nh using the equation: esl = v esl(step) i l ? t on ? t off t on + t off ? ? ? ? ? ? if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), the result - ing waveform looks resistive again, as shown in figure 9. figure 7. two different methods of sensing current figure 8. voltage waveform measured directly across the sense resistor figure 9. voltage waveform measured after the sense resistor filter, c f = 1nf, r f = 100 (7b) using inductor dcr to sense current check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use lt c7821 rev a 7821 f07a c f r f r f r s esl c c i sns + i sns ? l pgnd intv cc bg2 sw3 boost3 tg2 mid_sense mid v out sense resistor plus parasitic inductance m3 c f ? 2r f < esl/r s pole-zero cancellation filter components placed near sense pins (7a) using a resistor to sense current m3 m4 d c r c c m4 c out 7821 f07b c1 r2 l dcr c i sns + i sns ? pgnd d intv cc bg2 sw3 boost3 tg2 mid_sense mid v out inductor place r1 next to inductor c place c1 near sns + , sns ? pins r1 500ns/div v sense 5mv/div 7821 f08 500ns/div v sense 5mv/div 7821 f09 r c c out
18 for more information www.analog.com the equation to determine the esl. however, do not over filter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense. the filter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin connected to the sense resistor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the LTC7821 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 7b . the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing. if the external r1|| r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is : r sense(equiv ) = 50mv i (max ) + i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table. next, determine the dcr of the inductor. where provided, use the manufacturer s maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c . to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv ) dcr(max) at t l(max ) c1 is usually selected to be in the range of 0.047f to 0.47f . this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense pins 1.2a current. t l(max) is the maximum inductor temperature. the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: r1||r2 = l (dcr at 20 c) ? c1 the sense resistor values are: r1 = r1||r2 r d ; r2 = r1? r d 1C r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss _ r1 = v mid C v out ( ) ? v out r1 where v mid is half the voltage of v in . ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1 . however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. t o maintain a good signal to noise ratio for the current sense signal, use a minimum v sense of 10mv for duty applications information lt c7821 rev a
19 for more information www.analog.com cycles less than 40%. for a dcr sensing application, the actual ripple voltage will be determined by the equation: v sense = v mid C v out r1? c1 ? v out v mid ? f osc slope compensation and inductor peak current slope compensation provides stability in constant fre - quency architectures by preventing subharmonic oscilla - tions at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally , this results in a reduction of maximum inductor peak current for duty cycles > 40%. however, the LTC7821 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i ripple = v out v mid ? v mid C v out f osc ? l lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) for a duty cycle less than 40%. note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v mid C v out f osc ? i ripple ? v out v mid for duty cycles greater than 40%, the 10mv current sense ripple voltage requirement is relaxed because the slope compensation signal aids the signal-to-noise ratio and because a lower limit is placed on the inductor value to avoid subharmonic oscillations. to ensure stability for duty cycles up to the maximum of 95%, use the following equation to find the minimum inductance. l min > v out f sw ? i load(max ) ? 1.4 where l min is in units of h f sw is in units of mhz inductor core selection once the inductance value is determined, the type of in - ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is ver y dependent on inductance selected. as inductance increases, core losses go down. unfortunately , increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet selection four external power mosfets must be selected for the LTC7821 . the gate drive voltages to these mosfets are derived from the intv cc voltage, which is typically 5.8v. hence logic-level threshold mosfets must be selected. only the upper-most mosfet requires a bv dss greater than v in , because this mosfet sees the full v in voltage during start-up. the other mosfets, m2 to m4, need only have a bv dss greater than v in /2. during operation, the type of switching also impacts how each power mosfet is selected. m1 and m2 operate in soft switching mode, so they should have low qoss ? applications information lt c7821 rev a
20 for more information www.analog.com rds on product. m3 and m4 operate in a manner similar to traditional buck converter, with m3 hard switching while m4 operates in zero voltage switching (zvs). therefore m3 and m4 should be chosen with the lowest (qgd ? rds on ) and (qg ? rds on ) product, respectively. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (see figure 10). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the voltage, but can be adjusted for different v ds voltage by multiplying the ratio of the application v ds to the curve specified v ds value. a way to estimate the c miller term is to take the change in gate charge from point a-and-b on a manufacturers data sheet and divide by the specified v ds voltage. c miller is the most important selection criteria for determining the transition loss term in the mosfet m3 but is not directly specified on mosfet data sheets. c rss and c oss are specified sometimes but definitions of these parameters are not included. in a traditional synchronous buck converter, the current flowing through the upper and lower mosfet is the same as the inductor current (see figure 11). in the hybrid topol - ogy of the LTC7821, the mosfet and inductor currents do not match, because the capacitors play a role in energy transfer to the output. in the first phase (see figure 12a), m1 and m3 are on and the capacitor c mid provides part of the inductor cur - rent via m3 . the rest of the inductor s current is provided through c f ly via m1. if the capacitance of c f ly is the same as c mid , then the inductors current is equally supplied by both capacitors as shown in figure 12b. therefore compared to the traditional buck converter with the same amount of inductor current, less current flowing through m3 means lower switching loss and conduction loss. since m3 switches hard, this reduction in current reduces the switching loss significantly. in the 2nd phase, m2 and m4 are on (see figure 13a). in this phase, m4 not only has to supply the full inductor applications information figure 11. mosfets current of traditional synchronous buck converter figure 10. gate change characteristic gate-to-drain capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a-to-b while the curve is flat) is specified for a given v ds drain + ? ? + ? + lt c7821 rev a 7821 f11 m3 current m4 current v miller effect a b q in c m3 miller = (q b ? q a )/v ds v in v m4 7821 f10 gs v ds v gs l1 c1 m3 current flow m4 current flow inductor current time
21 for more information www.analog.com applications information figure 12. first phase m1 and m3 current flow figure 13. second phase m2 and m4 current flow lt c7821 rev a 1/2i l m1 and m3 current if c f ly = c mid (12a) current path of m1 and m3 (12b) m1 and m3 current magnitude 7821 f12 m1 m2 m3 m4 l1 l1 c1 c f ly c mid (13a) current path of m2 and m4 (13b) m2 and m4 current magnitude m1 m2 c1 m3 m4 current time 7821 f13 inductor current m4 current m2 current c f ly c mid current time inductor current i l
22 for more information www.analog.com applications information current, but also carries the balancing current that flows between c f ly and c mid due to an imbalance of voltage between the two capacitors at the end of phase 1. there - fore m4 has an increase in conduction losses compared to its counterpart in a traditional buck converter . the current flowing through m2 is dependent on the voltage differential between the capacitors, their esr, r dson of m2 and m4 , and inductance of the mosfets, capacitors, and board traces (see figure 13b). when the controller is operating in continuous mode the duty cycles for m1, m3, m2 and m4 are given by: m1, m3 switch duty cycle = 2 ? v out v in m2, m4 switch duty cycle = v in C 2 ? v out v in the power dissipation of m1 and m3 is given by: p m1 = i max ? c fly c fly + c mid ? ? ? ? ? ? 2 2 ? v out v in ? ? ? ? ? ? 1 + d ( ) r ds(on) p m3 = i max ? c mid c fly + c mid ? ? ? ? ? ? 2 2 ? v out v in ? ? ? ? ? ? 1 + d ( ) r ds(on) + v in 2 ? ? ? ? ? ? 2 i max ? c mid 2 ? c fly + c mid ( ) ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v th(min) + 1 v th(min) ? ? ? ? ? ? ? f where d is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), and v in is the input supply. v th(min) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. if the switching loss contribution of p m3 is relatively small compared to its conduction loss, then the overall power dissipation (p m1 + p m3 ) will be the lowest when c f ly = c mid . the power dissipation of m2 and m4 is harder to calcu - late, because the current flowing through these mosfets exhibits a 2nd order system response due to the presence of parasitic package inductance of the mosfet s and ca - pacitors, esr of the capacitors, r ds(on) of the mosfets and the capacitance of c mid and c f ly . complicating the matter is that the current could exhibit overdamped, criti - cally damped or underdamped characteristics, depending on the rlc values mentioned above ; this would impact the rms current significantly. use adi/ltc power tool to help select m2 and m4. with the rms current flowing through m2 and m4 deter - mined, the power dissipation is given by: p m2 = i 2 rms2 ? 1 + d ( ) r ds(on) p m4 = i 2 rms4 ? 1 + d ( ) r ds(on) c f ly and c mid selection in this hybrid topology, capacitors c f ly and c mid are part of the energy transfer elements. therefore ceramic capacitors are attractive since they have the lowest esr. however, care should be taken when choosing this type of capacitor. during operation the dc voltage across the c f ly and c mid is approximately half the v in supply, therefore the voltage rating of the capacitors should be greater than that. as a general rule, select the voltage rating of the capacitor to be twice the operating voltage of the capacitor. for the same voltage rating and capacitance, a larger case size will have a lower failure rate. in addition, the operating temperature of the capacitors needs to be considered. for operating temperature above 85c, capacitors with the x7r dielectric need to be used while x5r dielectric is adequate for operation below 85c. for long term reliability of the capacitor, keep the tem - perature rise of the capacitor to be below 20c, preferably 10 c . the temperature rise of the capacitor is dependent on the amount of rms current through the capacitor and the operating frequency. consult the manufacturer s data sheet for this data. lt c7821 rev a
23 for more information www.analog.com applications information ceramic capacitors also have a large voltage coefficient, losing close to half their capacitance when the dc bias across a given capacitor is half its rated voltage. the dc bias effect on a capacitor is greater when the case size is smaller. factor in these effects when deciding on the capacitance. the ripple voltage of c f ly and c mid is given by: v cfly _ ripple = i out ? t on 2 ? c fly v cmid _ ripple = i out ? t on 2 ? c mid where i out is the output current and t on is the on-time of m1 and m3. the ripple voltage on c f ly and c mid , (v cfly_ripple , v cmid_ ripple ), contributes significantly to the power dissipated in m2 and m4 (see power mosfet selection section). as a good starting point, select enough capacitance such that the ripple on each capacitor is less than 1% of the dc bias voltage of the capacitor. for example, if the dc bias voltage of the capacitor is 24v, keep the ripple to be less than 240mv . for the lowest conduction loss of mosfets m1 and m3 (see power mosfet selection section), select the capacitance of c mid to be the same as that of c f ly . schottky diode and bootstrap capacitors selection three diodes are used to form a charge pump circuit to provide the drive voltages for mosfets m1 to m3. figure 14 shows the diodes configuration. the voltages across the following bootstrap capacitors are approximately : v bst1_sw1 = v intvcc C v f_d1 C v f_d2 C v f_d3 v bst2_mid = v intvcc C v f_d2 C v f_d3 v bst2_sw3 = v intvcc C v f_d3 where v f_dx is the forward voltage of diode x. figure 14. external charge pump lt c7821 rev a d1 d2 d3 LTC7821 v in tg1 tg2 bg1 bg2 sw1 m1 mid sw3 intv cc m2 m3 m4 cbst1 cbst2 cbst3 7821 f14
24 for more information www.analog.com applications information to obtain the most translation in voltage from v intvcc to drive m1, schottky diodes are recommended. the reverse voltage seen by each of the schottky diodes is approximately: v r _ diode ? v in 2 pay attention to the leakage current when selecting the forward drop of the diodes. in general, the lower the forward drop for the same amount of current flowing through the diode, the higher the leakage current. as these diodes will be operating with large reverse bias for high v in applications, the leakages are higher, especially at higher operating temperatures. the charge pump diodes operate as conduits for transfer - ring charge from one capacitor to another and as such are subjected to transient current rather than a dc current. hence peak forward surge rating is more important than the average current rating. a surge rating of 750ma is a good starting point. since the bootstrap capacitor acts as a supply for the mosfet s driver, select large enough capacitance so that the voltage does not droop considerably when the mosfets are being turned on. as with the c miller esti- mation described in the power selection section, the user can use the same graph to obtain the total gate charge for a given gate drive voltage. this can then easily converted to its equivalent gate capacitance by : c g = q g v gs if the bootstrap capacitor voltage is not allowed to droop by more than 1%, then: c bst 99c g besides acting as a supply for their respective mosfet drivers, c bst2 and c bst3 also serve as charge pump ca - pacitors. as a good starting point, size c bst2 and c bst3 as follows: c bst3 2c bst2 2c bst1 soft-start and tracking the LTC7821 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when configured to soft-start by itself, a capacitor should be connected to its track/ss pin and ground. when run pin voltage is below 1.22v, the track/ ss is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.22v, the controller powers up and a soft-start current of 10a begins to flow out of the track/ss pin. however, the track/ss will start charging its soft-start capacitor only after charge balance is completed and the associated active pull-down of the track/ss is released. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the track/ss pin. current fold-back is disabled during this phase to ensure smooth soft-start or tracking. depending on whether the ext_ref feature has been invoked or not, the soft-start or tracking range is defined to be either the voltage range from 0v to 0.8v or 0v to v ext_ref on the track/ss pin. the total soft-start time can be calculated as: t soft ? start = 0.8 or v ext _ ref ( ) ? c ss 10a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to track/ss = 82.5% of 0.8v or v ext_ref . output voltage tracking the LTC7821 allows the user to program how its output ramps up and down by means of the track/ss pins. through this pin, the output can be set up to either coin - cidentally or ratio-metrically track another supply s output, as shown in figure 15. in the following discussions, v out1 refers to another supplys output (master channel) while v out2 refers to the LTC7821 output (slave channel) that tracks v out1 . to implement the coincident tracking in figure 15a, connect an additional resistive divider to v out1 and connect its midpoint to the track/ss pin of the LTC7821. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 16a. in this tracking mode, v out1 must be set higher than v out2 . lt c7821 rev a
25 for more information www.analog.com applications information figure 17. output voltage set by ext_ref pin figure 15. two different methods of output voltage tracking figure 16. setup for coincident and ratio-metric tracking to implement the ratiometric tracking in figure 15b, the ratio of the v out2 divider should be exactly the same as the master channels feedback divider ratio shown in figure 16b. in order to track down another channel or supply after the soft-start has successfully reached 82.5% of 0.8v or v ext_ref , it is recommended to set the LTC7821 into force continuous mode operation by setting the mode/ pllin = 0v . for no load condition, the LTC7821 should be in force continuous mode to ensure good tracking of the master supply. by selecting different resistors, the LTC7821 can achieve different modes of tracking including the two in figure 15. the ratio-metric mode uses one less pair of resistors compared to the coincident mode but has lesser output accuracy on v out2 and is also fully coupled to any varia - tions in v out1 . in both modes, there is an error in output voltage setting cause by the pin current of track/ss. to minimize this error, use smaller resistor values in the divider. output voltage setting the LTC7821 uses its internal reference of 0.8v when the v ext_ref 1.3v. the output voltage is given by: v ou t = 0.8 ? 1 + r2 r1 ? ? ? ? ? ? if the applied voltage to the ext_ref is less than 1.3v, then v out will track ext_ref voltages between 0.4v and 0.9v, as indicated by the characteristic in figure 17. lt c7821 rev a (15a) coincident tracking (15b) ratio-metric tracking 7821 f15 r3 (from LTC7821) external supply (from LTC7821) external supply r4 r1 output voltage r2 r3 r4 r1 r2 r3 r4 v out1 v out2 to output voltage track/ss pin of LTC7821 to v fb1 pin to v fb2 pin v out1 time v out2 to track/ss pin of LTC7821 to v fb1 pin to v fb2 time pin (16a) coincident tracking setup (16b) ratio-metric tracking setup 7821 f16 v out 0.4v 7821 f17 0.9v 0.4?(1+r2/r1) 0.9?(1+r2/r1) v out1 v ext_ref v out2 v out1 v out2
26 for more information www.analog.com applications information due to its unique architecture, the optimal efficiency for the LTC7821 is when v out ? v in /4. for applications that demand optimal efficiency within a range of v in , ext_ref could be used to track this v in variation while maintaining a 4:1 step down ratio at the output. in this type of setup the output voltage will also change with the input. figure 18 shows a 48v to 12v setup that accounts for v in varia- tion between 36v to 72v. minimum v out during the c f ly capacitor balancing phase, a current of approximately 40ma (i src ) flows out of sw1 node to charge the flying capacitor c f ly to v in /2. to prevent this current from charging c out , an identical amount is sunk (i snk ) away at sw3 node. figure 21 shows the current path. a minimum output voltage of 2v is needed to ensure the complete sinking of the sourcing current. in applications that need the output to be regulated below 2v, a resistive load can be added across v out to ensure that the voltage will not exceed the regulated value during the capacitor balancing phase. the resistive load value is given by: r load < v out 0.04 select r load to be about 70% of the calculated value. hys_prgm voltage the voltage on the hys_prgm pin sets a window (thresh - old) centered on v in /2 for fault protection purpose. during operation, if the voltage across mid_sns and ground devi - ates beyond this window, a fault is indicated and capacitor balancing begins. therefore setting the correct window is important as it adds another layer of protection to the power system. in continuous switching, the first order approximate impedance at mid is given by : z mid = 1 8 ? c fly ? f sw ? e d1? t s 2 ? t 1 + e C d1? t s 2 ? t 1 e d1? t s 2 ? t 1 C e C d1? t s 2 ? t 1 + e d 2 ? t s 2 ? t 2 + e C d2 ? t s 2 ? t 2 e d2 ? t s 2 ? t 2 C e Cd2 ? t s 2 ? t 2 ? ? ? ? ? ? ? ? ? ? = 1 8 ? c fly ? f sw ? coth d1? t s 2 ? t 1 ? ? ? ? + coth d2 ? t s 2 ? t 2 ? ? ? ? ? ? ? ? ? ? where: t s = switching period f sw = switching frequency d1 = duty cycle of mosfet 1 and 3 d2 = duty cycle of mosfet 2 and 4 t1 = (r on1 + r on3 + r esr_fly ) ? c f ly t2 = (r on2 + r on4 + r esr_fly ) ? c f ly r onx = resistance of mosfet x in figure 18. output voltage to track v in in 4:1 ratio the minimum output voltage that can be set for the LTC7821 is limited by the charge balancing circuit and its minimum on-time. the charge balancing circuitry requires at least 2v on the output and is independent of v in . the minimum on time determines the minimum v out by: v ou t(min) = v mid ? t on(min) t s where t s is the switching period. hence, v ou t(min) = max 2.5v, v mid ? t on(min) t s ? ? ? ? ? ? the internal charge balancing circuitry requires a minimum differential voltage between v in /2 and v out of 2.5v to op - erate. this limits the maximum output voltage setting to: v ou t(max ) = v in 2 C 2.5 for applications where the load is resistive and acts like a discharging path, the minimum v out can be lowered to 0.8v. lt c7821 rev a 7821 f18 v out to v fb pin v in to r5 ext_ref pin (36v to 72v) (9v to 18v) 464k r6 5.9k r1 82.5k r2 4.32k
27 for more information www.analog.com applications information figure 19a shows a typical LTC7821 output stage setup while 19b shows the equivalent circuit. note that m3 and m4 form the buck converter switches, taking its power from mid, with its voltage given by: v mid = v in 2 C i out ? v out v in ? 1 h ? ? ? ? ? ? ? z mid where h = efficiency of the buck converter. a good conservative number to use for h is 0.9. the above equation gives us the average mid voltage and does not include the ac ripple on it. the c mid ripple voltage is given by (see c f ly and c mid selection section): v cmid _ ripple = i out ? t on 2c mid therefore the maximum deviation of mid voltage from v in /2 is given by: v mid _ ideal = v in 2 C v mid C i out ? t on 2c mid use the above equation as a guideline to set the hys_prgm voltage. design example a 48v to 5v, 25a operating at 500khz application is used as an example. since the output current is high, dcr sensing is used to regulate the current loop. for 500khz operation, a 68k resistor is connected from freq to ground. since v in = 48v , infineon bsc027n06ls5 is chosen for m1. this is an 60v mosfet. for m2 to m4, 30v mosfets are sufficient for this application. for m2 and m3 , infineon b sc032n04 ls are selected and an infineon b sc014n04lsi is selected for m4. m1, m3 duty cycle = 5 24 = 0.208 t off = (1C 0.208) ? 2s = 1.58s with inductor current ripple initially scaled to 40% of output current, i l = 0.4 ? 25 = 10a, hence, l = v out ? t off i l = 5 ? 1.58 ? 10 C 6 10 = 0.79h an inductance of 0.9h is selected (coilcraft ser2011- 901l) instead and this give i l = 8.8a . the rms current through the inductor is: i rms _ l = i 2 out + i 2 l 12 ? ? ? ? ? ? = 25 2 + 0.4 2 12 = 25.2a from the manufacturer data sheet, the rise in temperature of the inductor is 15c . however, this rise does not account for the conduction of heat from the mosfets through the pcb that increases the overall inductors temperature. depending on how the board is being laid out and how much air flow is applied, the net increase in temperature could be higher. for this design example, assume the net temperature rise to be 50c. the typical dcr of the inductor is typically 1.2m with a maximum of 1.34 m and with a 50c rise in temperature and assuming the temperature coefficient of the dcr at 0.4%/c, the maximum dcr is: r dc = 15 c = 1.34 ? 1 + 0.4 ? 50 100 ? ? ? ? ? ? ? 10 C 3 = 1.61m lt c7821 rev a
28 for more information www.analog.com applications information figure 19. LTC7821 output setup ? + ? + ? + ? + lt c7821 rev a m3 m4 (19a) LTC7821 output setup c mid c f ly v v r filt c filt c out (19b) LTC7821 thevevin output equivalent l r fb1 r fb2 f(hys_prgm) tg1 sw1 bg1 mid_sns mid tg2 r filt v in LTC7821 bg2 v in 2 v fb 7821 f19 m3 l m4 c filt v1 v1 c out r fb1 r fb2 f(hys_prgm) mid_sns mid LTC7821 v in v out 2 z mid tg2 bg2 c mid v in 2 v out v fb m1 m2
29 for more information www.analog.com applications information with a v sense = 50mv , the dcr will set the peak inductor current to be 31a. with a ripple i l of 8.8a, the application will provide 25a of output current. for the sensing network, select c1 = 0.22f, then: r8 = l c1? dcr = 3.4k for the design, a 3.32k resistor is used. the next components to select are the c mid and c f ly . in this example, c mid = c f ly to maintain ripple at c mid and c f ly to be 1% of its dc bias: v cmid and v cfly = 0.01? 24 = 240mv hence, c fly = i out ? t on 2 ? v cmid = 25 ? 0.42 ? 10 C 6 2 ? 0.24 = 21.88f = c mid the voltage rating chosen for these capacitors is 50v and even with this rating, the actual capacitance is lower due to its voltage coefficient. 6 10f is chosen for each c mid and c f ly . with this value of c mid , the voltage ripple at mid is now: v cmid _ ripple = i out ? t on 2 ? 60 ? 10 C 6 = 87.5mv the next components to select are the bootstrap capaci- tors. for m1, the gate charge needed to charge its gate from v gs = 0v to 6v is: q g = 9nc therefore, its equivalent gate capacitance is: c g = q g v gs = 1.5nf hence, c bst1 = 99 ? c g = 0.15f use, c bst1 = 0.22f c bst2 = 0.47f c bst3 = 1f for the schottky diodes, centrals cmdsh-4 are used. from the manufacturer data sheet, the r dson of m1 to m4 are 3.1m, 3.2m, 3.2m, and 1.4m respectively. the equivalent impedance at mid node, z mid , can be calculated to be: z mid = 1 8 ? c fly ? f sw ? coth d1? t s 2 ? t 1 ? ? ? ? ? ? + coth d2 ? t s 2 ? t 2 ? ? ? ? ? ? ? ? ? ? ? ? = 18.15m this will result in an average mid voltage of: v mid = v in /2 C (31a ? 18.15m) = 23.437v factoring in the ripple voltage on c mid , the minimum v mid is: v mid _ min = 23.437 C 0.0875 = 23.35v this is 650mv lower than the ideal voltage of 24v at mid point. therefore set the voltage at hyst_prgm pin to be 1v with a resistor of 100k. the completed circuit for this design example is shown in figure 20. lt c7821 rev a
30 for more information www.analog.com applications information minimum on-time considerations minimum on-time t on(min) is the smallest time duration that the LTC7821 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < 2 ? v out v in (f) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC7821 is approximately 210ns, with reasonably good pcb layout, minimum 30% inductor current ripple and at least 10mv C 15mv ripple on the current sense signal. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time increases. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skip - ping can occur with correspondingly larger current and voltage ripple. multiphase operation for high output power applications, two LTC7821 's can be paralleled to create a dual phase single output configura - tion. figure 22 shows the key signal connections between the two LTC7821s. lt c7821 rev a
31 for more information www.analog.com applications information figure 20. a 48v to 5v, 500khz, 25a application + + efficiency and power loss for 48v to 5v vs load current lt c7821 rev a c in 100f 100v 88 91 94 97 100 0 1 2 3 4 m1 bsc027n06ls5 5 6 7 8 9 10 efficiency (%) power loss (w) 7821 f20a m2 bsc032n04ls m3 bsc032n04ls m4 bsc014n04lsi r2, 1k c6, 0.47f c1 0.1f r5 10k r4 10k ser2011-901l l1, 0.9h c9 1nf c10 0.1f c out 150f 16v 2 16svpc150m 1k r3 c5 0.1f c7, 0.1f c3 10f r6, 68k r7, 100k c f ly 10f 50v 6 grm32er71h106ka12 r8, 3.3k c11 0.22f v in_sense v in temp timer run freq hys_prgm ext_ref r1 6.04k fault pgood mode/pllin i th track/ss extv cc v fb i sns + i sns ? pgnd cbst1, 0.22f intv cc bg2 sw3 boost3 tg2 mid_sense mid boost2 bg1 sw1 cbst2 0.47f boost1 LTC7821 7821 f20 tg1 v in 48v intv cc v out 5v 25a d1 cmdsh-4 cmdsh-4 cbst3, 1f d2 d3, cmdsh-4 intv cc 8v pgood fault c8 470pf c mid 10f 50v 6 grm32er71h106ka12 c4 2.2f 100v 6 pin not used in this circuit: clkout cv cc r fb1 , 22.6k r fb2 4.32k v in = 48v v out = 5v f sw = 500khz ccm load current (a) 1 5 9 4.7f, 16v 13 17 21 25 70 73 76 79 82 85
32 for more information www.analog.com applications information figure 21. c f ly prebias current path figure 22. connection of key signals of LTC7821 for dual phase operation lt c7821 rev a i th LTC7821 LTC7821 run clkout track/ss v fb v out gnd i th v in run v in v out i src i snk c v in f ly c out r1 r2 l LTC7821 v fb sw1 mode/pllin sw3 7821 f21 track/ss v fb v out gnd 7821 f22
33 for more information www.analog.com applications information + + 1f 0.47f 0.22f 100k 68k 0.1f 0.1f figure 23. 500khz 48v to 9v, 20a step-down converter efficiency and power loss for 48v to 9v vs load current lt c7821 rev a c in 100f 4 6 8 10 12 efficiency (%) power loss (w) 7821 f23a m1 m2 m3 m4 r2 100k c6 c1 1f r5 10k r4 10k l1, 2h c9 6.8nf c10 0.1f 1k r3 c5 0.1f rfb1 60.4k rfb2 5.9k c7 c3 10f x2 r6 c f ly 10f 8 r7 r8 6.81k c11 0.22f v in_sense v in temp timer run freq hys_prgm r1 29.4k ext_ref fault pgood mode/pllin i th track/ss extv cc v fb i sns + i sns ? cb1 pgnd intv cc bg2 sw3 boost3 tg2 mid_sense mid boost2 bg1 cb2 sw1 boost1 LTC7821 7821 f23 tg1 v in 48v intv cc v out 9v 20a d1 d2 cb3 d3 pgood fault c8 100pf c2 10f 8 c out 150f 2 c4 2.2f 6 pin not used in this circuit: clkout m1: infineon bsc057n08ns3 m2, m3: infineon bsc032n04ls m4: infineon bsc014n04lsi l1: coilcraft ser2011-202ml cfly, c2: murata grm32er71h106ka12 d1 to d3: central semiconductor cmdsh-4 cv cc v out = 9v v in = 48v ccm f sw = 500khz load current (a) 2 6 9 13 16 4.7f 20 88 90 92 94 96 98 100 0 2
34 for more information www.analog.com information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/product/LTC7821#packaging for the most recent package drawings. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) lt c7821 rev a
35 for more information www.analog.com revision history rev date description page number a 04/18 corrected note 4 to note 5 on ec table corrected conditions for i vin , vin_sense and g m remove references to timing diagram update run pin description corrected current source on run pin from 10a to 1a fixed text formatting on rd symbol updated soft-start time formula for clarity corrected c11 to c1 3 3 5 9 11 18 24 28 lt c7821 rev a
36 for more information www.analog.com ? analog devices, inc. 2017-2018 d16842-0-4/18( a ) www.analog.com related parts typical application part number description comments ltc7820 fixed ratio high power inductorless (charge pump) dc/dc controller 6v < v v in 72v, fixed 50% duty cycle, 100khz to 1mhz switching frequency (4mm 5mm) ufd package ltc3895 150v low i q , synchronous step-down dc/dc controller 4v v in 140v, 150v pk , 0.8v v out 24v, i q = 50a, pll fixed frequency 50khz to 900khz ltc3810 100v synchronous step-down dc/dc controller constant on-time valley current mode 6.2v v in 100v, 0.8v v out 0.93v in , ssop-28 ltc3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle 4v v in 60v, 0.8v v out 24v, i q = 50a, pll fixed frequency 50khz to 900khz lt3840 60v, low i q , synchronous step-down controller with integrated buck-boost bias voltage regulator 2.5v v in 60v, 1.23v v out 60v, i q = 75a, synchronizable fixed frequency 100khz to 600khz ltc3892/ ltc3892-1 60v low i q , dual, 2-phase synchronous step-down dc/dc controller with 99% duty cycle 4v v in 60v, 0.8v v out 0.99v in , pll fixed frequency 50khz to 900khz, adjustable 5v to 10v gate drive, i q = 29a ltc7813 low i q , synchronous boost + buck dc/dc controller 4.5v (down to 2.2v after start-up) v in 60v, 0.8v v out 60v, adjustable 5v to 10v gate drive, i q = 33a lt8705a 80v v in and v out synchronous 4-switch buck-boost dc/dc controller 2.8v v in 80v, 100khz to 400khz programmable operating frequency (5mm 7mm) qfn-38 and tssop-38 ltc3886 60v dual output step-down controller with psm 4.5v v in 60v, 0.5v v out (0.5%) 13.8v, input current sense, i 2 c/pmbus interface with eeprom and 16-bit adc ltc3871 bidirectional multiphase synchronous buck or boost controller regulation of input voltage, output voltage or current v high up to 100v, v low voltages up to 30v high efficiency 500khz 2-phase 48v to 12v at 40a step-down converter + + v out v out 12v 8v to extv cc pin of LTC7821 v in lt c7821 rev a m1 bg2 sw3 boost3 tg2 mid_sense mid boost2 bg1 sw1 boost1 m2 tg1 intv cc2 v8 l2, 2h c fly2 10f 8 c b4 0.22f c13 0.1f c12 1f c b5 0.47f c b6 1f m3 cv cc1 4.7f m5 m8 m7 m6 r16 6.81k r15, 100k r14, 100k r10, 100 r13, 1k m4 c22 0.22f d4 d5 d6 c17 0.1f c18 10f 8 r9 : murata prf15bc102rb6rc m1, m5: infineon bsc057n08ns3 m2, m3, m6, m7: infineon bsc032n04ls m4, m6: infineon bsc014n04lsi r2, 100 l1, l2 : coilcraft ser2011-202ml c fly1 , c fly2 , c2, c18: murata grm32er71h106ka12 d1 to d6 : central semiconductor cmdsh-4 ltc3621 c6, 0.1f r9 r11 55.57k 8v c1 1f l1, 2h r5 10k r4 10k c10 0.1f c9 0.015f c out 150f 4 v out 12v, 40a r3, 1k r fb1 60.4k r fb2 4.32k c5 0.1f c fly1 10f 8 c7, 0.1f c3 10f 4 r6, 68k r7, 100k r8 6.81k c11 0.22f v in_sense v in temp clkout r1 14.7k timer run freq hys_prgm ext_ref fault pgood mode/pllin i th track/ss c b1 0.22f extv cc v fb i sns + i sns ? pgnd intv cc bg2 sw3 boost3 tg2 c b2 0.47f mid_sense mid boost2 bg1 sw1 boost1 7821 ta02 tg1 intv cc1 d1 c b3 1f d2 d3 intv cc1 intv cc2 8v pgood fault c8 100pf c2 10f 8 c4 2.2f 6 cv cc 4.7f v in 36v to 72v v in_sense v in temp timer run freq hys_prgm ext_ref fault c in 100f 2 pgood mode/pllin i th track/ss extv cc v fb i sns + i sns ? pgnd intv cc

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